The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Components of an electronic or computing system are often integrated into a System-on-Chip (SoC) as intellectual property (IP) blocks, decreasing the size, cost, and power requirements of the system while providing equivalent features or functionality. Fast time-to-market pressures of highly complex SOCs and the increasing need to integrate new product differentiating features between product generations have forced SOC developers to integrate increasing number of functional IP blocks into these SoCs resulting in increased design complexity, compressed design schedules, and constrained design resources. To handle these trends SOC developers use third party IP blocks and a standard common bus architecture to connect these IPs for SoC development and design. These IP blocks are designed for standard interfaces, thus providing ease of integration into the SoC design saving time and resources.
Verification of an SoC design containing these third party IP blocks, however, is typically difficult as knowledge of the internal micro-architecture of the third party IP blocks is limited. Any assumptions made in the IP design micro-architecture which results in a unique behavior on its interface cannot be adequately exercised through pre-Si simulations. These assumptions are typically triggered when real world applications are run that cause these interesting interconnect stress conditions. Real world applications cause unique loading conditions thereby resulting in complex interconnect handshake behavior signature between the IPs which exposes untested areas. These untested areas can cause incorrect behavior of either the IP blocks or the interconnect logic and it manifests as functional failures in the silicon SoC as system hangs, lock-ups, and/or degraded performance. Debugging and root-cause analysis of these issues during post-Si validation is extremely difficult and time consuming causing a lot of expenditure of resources and time.